Germanium on silicon heteroepitaxy for high efficiency photovoltaic devices

[摘要] Optoelectronic devices based on III-V direct gap semiconductors enable efficient energy conversion for photovoltaic cells, light emission for LEDs, and on-chip communication via various microphotonic components. However, widespread adoption of III-V solar cells is limited by the expensive Germanium and III-V standard substrates required, while monolithic integration of III-V devices with Silicon CMOS circuitry is not yet well established. III-V solar cell cost reduction and direct Si/III-V integration can both be realized by depositing a thin layer (e.g. 1 [mu]m) of high quality Ge on relatively inexpensive Si substrates for which the decreased cost is due to Si;;s greater material abundance and larger possible wafer diameters. Efficient device performance will be retained if the Ge layer maintains a sufficiently low threading dislocation density (TDD) that does not adversely effect carrier lifetimes in epitaxially deposited III-V layers that inherit the Ge film;;s TDD. Assuming recombination at dislocations is carrier diffusion limited, an acceptable limit for most applications is below 10⁶ cm-² due to typical minority carrier diffusion lengths of ~ 10 [mu}m in III-V materials. However, direct deposition of Ge on Si will initially generate a TDD as high as 10¹² cm-² to plastically relax the 4.2% lattice mismatch between the two materials. State of the art approaches can reduce the TDD in large-area films to 10⁶ cm-² by including a 10+ m thick SiGe compositionally graded buffer, while TDD reduction in thinner films (e.g. 1 [mu]m) is limited to 10⁷ cm-² after cyclic annealing which enhances dislocation fusion and annihilation reactions. By introducing Ge film edges spaced approximately 10 [mu]m apart to serve as dislocation sinks during dislocation glide, the TDD has been reported to further decrease to 2:310⁶ cm-² in 1 m thick patterned Ge. However, these films are limited to areas too small for photovoltaic cells, and the sinks appear ineffective for thread reduction at the edges of faceted, selectively grown Ge. Thus, no solution has previously existed for a thin Ge-on-Si film grown over large areas that achieves a TDD of 10⁶ cm-² or below. This thesis first explores the limitations to dislocation reduction by sinks in selectively-grown Ge and provides structure and fabrication modifications to enable patterned Ge films with a TDD below 10⁶ cm-² throughout the patterned region. To use these films for large-area applications, overgrowth and coalescence of patterned Ge films are then evaluated in different pattern designs to determine the structures that optimize coalescence in terms of throughput as well as simultaneously avoid generation of additional defects as a result of coalescence. TDD reduction in patterned Ge films by glide to film edges requires uniform resolved shear stresses and minimum dislocation pinning during cyclic annealing. Because film facets allow for elastic relaxation of the applied thermal strain, the process of selective growth must be reversed: blanket Ge is to be grown instead to avoid faceting, followed by sidewall etching and filling before the cyclic anneal. Thermal expansion mismatch between Ge and the sidewall causes undesirable shear stress components while repulsive image forces are created if the sidewall surface;;s shear modulus is greater than that of Ge. Therefore, the ideal sidewall is primarily composed of Ge, separated from the primary Ge film by a thin SiO₂ layer. Monte Carlo simulations of dislocation glide were developed to estimate the limitations of glide due to the pinning effect of orthogonal dislocations. For small mesa widths w (or more generally, the spacing between adjacent dislocation sinks), TDD was found to scale with wa with a 4. The threshold of the small width regime and the value of a both increase for greater applied thermal stresses and thicker Ge films. Due to the high surface energy of the Ge/SiO₂ interface, lateral overgrowth and film coalescence do not readily occur. The rate was observed to strongly correlate with the Ge film perimeter concavity, delayed at convex mesa corners while relatively promoted at the ends of isolated SiO₂ lines surrounded by a concave Ge film perimeter. Ge mesa arrays were staggered to eliminate regions entirely dependent on overgrowth from mesa corners, decreasing the growth time until complete coalescence by at least 50% as compared to a regular gridded array. The faster overgrowth rates over isolated SiO² lines was observed to further increase for lines of reduced widths. Due to the facets that develop, orientation of SiO² lines relative to intersections of {111} planes with the substrate surface further affected overgrowth rates which maximized for slight offsets below 15°. Etch pit studies of coalesced, selectively-grown Ge films around SiO₂ sidewalls indicated a maximum TDD above the SiO² (6X10⁷ cm-² for staggered grids) while decreasing to 10⁷ cm-² further away in the film. As predicted by modeling, the dislocation pile-up near SiO₂ walls was due to inverted resolved shear stress and the reduced thickness at the Ge film edge. Significant improvement in TDD reduction is expected by these models if blanket Ge is instead grown, followed by etch and fill of sidewalls with additional Ge separated by a thin layer of SiO₂. While fabrication is more involved compared to the selective growth process, the structure will be successful at threading dislocation removal. With isolated line film edges of minimal width, oriented 5 from {111} surface intersection directions, the coalescence rate will be maximized. Coalescence-induced defects resulting from lattice misregistry over the SiO₂-coated Ge lines will be prevented as the Ge film is continuous at the line ends prior to overgrowth initiation. Assuming a pinning probability of 50%, a Ge film 1 [mu]m thick with a maximum distance between dislocation sinks < 6 [mu]m is expected to exhibit a TDD of 10⁵ cm-². At this density level, the performance of III-V devices will be unaffected, enabling both lower cost high efficiency III-V solar cells and LEDs as well as III-V/Si monolithic device integration. The multiple perspectives of analysis examined in this thesis are not limited to Ge-on-Si and can readily be applied to other high lattice-mismatched materials systems to obtain a low TDD surface in large areas while maintaining a buffer layer of minimal thickness.

[发布机构] Massachusetts Institute of Technology