Building blocks of a 250MHz bandwidth, 10-bit continuous-time delta-sigma analog to digital converter

[摘要] This thesis examines the design of a continuous time Delta-Sigma Analog to Digital Converter with the target performance to be 10-bit, 250MHz bandwidth with 200mW power dissipation.The design process involves choosing a top-level architecture and designing transistor-level blocks. The architecture is selected to be second-order, 3-bit with a 32 oversampling rate based on the ideal model simulation in MATLAB. The transistor-level circuits are designed in a BiCMOS technology. The SQNR result is 63.3dB and the power is 140mW.

[发布机构] Massachusetts Institute of Technology