LOW POWER FRACTIONAL-N PLLFREQUENCY SYNTHESIZER USING45NM VLSI TECHNOLOGY

[摘要] power has become one of the most important parameter in various communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. This paper presents the design and simulation of VLSI based low power fractional- N Phase locked loop frequency synthesizer for Bluetooth application. Among variety of frequency synthesis techniques , phase locked loop (PLL) represents the dominant method in the wireless communications industry. PLL, like most wireless communication technologies, is relatively new and has matured only in the last decade. This phase locked loop is designed using VLSI technology, which in turn offers high speed performance at low power. For improving the performance of fractional-N phase locked loop, Loop filter and Sigma-Delta modulator are the most important factors. The loop filter bandwidth limits the speed of switching time between the synthesized frequencies. The Periodic operation of dual modulus divider introduces phase noise in the PLL. To eliminate this phase noise, the digital Sigma-Delta modulator is used which generates a random integer number with an average equal to desired fractional ratio and pushes the spurious contents to higher frequencies. Noise shaping concentrates the quantisation noise produced at the PFD output into the higher frequencies where it is removed by the low-pass filter.

[关键词] Sigma-Delta modulator;Phase Noise, Phase Locked Loop;Fractional-N Frequency Synthesizer