Comparison between Low Power Clock Distribution Schemes in VLSI Design
[摘要] In the VLSI design low power is very important aspect at different level of designing. In this paper it is tried to review different factors affecting the power dissipation due to various clock distribution schemes like as single driver clock scheme and distributed buffers clock scheme. There are different tradeoffs in both of techniques such as size of buffers, number of buffers etc. Here it is also tried to showing various effects of particular clock distribution scheme such as clock skew, clock jitter.
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[关键词] Single driver clock scheme;Distributed buffer scheme;Clock jitter;Clock skew. [时效性]
