I-Sim: An Instruction Cache Simulator

[摘要] As clock rates and instruction-level parallelism use increase, cache/memory systems will have difficulty efficiently handling the access demands for data and instructions. To gain some insight into the potential performance bottleneck of an overworked instruction cache, a fully parameterized instruction cache simulator has been created. This paper describes the simulator's modeling, implementation, and usefulness.

[发布机构] HP Development Company

[学科分类] 计算机科学（综合）