SEE Tolerant Self-Calibrating Simple Fractional-N PLL

[摘要] We show a reliable on-chip clock multiplier for SEE testing or RHBD applications. Fine control of clock frequency is provided without complex delta-sigma schemes. Conflicts that can occur with voted PLLs are discussed, and how to avoid them.

[发布日期] 2010-04-12

[学科分类] 软件