Tool for a configurable integrated circuit that uses determination of dynamic power consumption

[摘要] A configurable logic tool that allows minimization of dynamic power within an FPGA design without changing user-entered specifications. The minimization of power may use minimized clock nets as a first order operation, and a second order operation that minimizes other factors, such as area of placement, area of clocks and/or slack.

[发布日期] 2011-08-30

[学科分类] 电子与电气工程