A High-Speed Low Power Multi-Modulus Frequency Divider based on TSPC logic using 55nm CMOS

[摘要] This paper presents an advanced architecture for programmable multi-modulus dividers (MMD) for high-speed and low-power synthesizers application in UMC 55nm CMOS technology. The proposed architecture used cascaded divide by divide-by-2/3. According to the design requirements, our MMD consists of 5 stages of the divide-by-2/3 dual-modulus dividers. The division ratio is ranged from 32 to 69 continually with the step of 1. Measurement results indicated a maximum operating frequency is 15GHz with 167 uW power consumption from a 1.2V supply voltage and occupied 50∗ 14 um2.

[发布机构] Tianjin Key Lab of Film Electronics and Communication Devices, School of Electrical and Electronic Engineering, Tianjin University of Technology, Tianjin, China^1;RF Microelectronics Corp., Tianjin, China^2

[效力级别] 无线电电子学 [学科分类] 材料科学（综合）

[关键词] Advanced architecture;CMOS technology;Frequency dividers;High-speed low-power;Maximum operating frequency;Multi-modulus divider (MMD);Proposed architectures;Supply voltages