Combined methods of tolerance increasing for embedded SRAM

[摘要] The abilities of combined use of different methods of fault tolerance increasing for SRAM such as error detection and correction codes, parity bits, and redundant elements are considered. Area penalties due to using combinations of these methods are investigated. Estimation is made for different configurations of 4K x 128 RAM memory block for 28 nm manufacturing process. Evaluation of the effectiveness of the proposed combinations is also reported. The results of these investigations can be useful for designing fault-tolerant "system on chips".

[发布机构] National Research Nuclear University, MEPhI (Moscow Engineering Physics Institute), Kashirskoe shosse 31, Moscow; 115409, Russia^1

[关键词] Area penalty;Combined method;Embedded SRAM;Error detection and correction codes;Fault-tolerant;Manufacturing process;Memory blocks;Parity bits