Low-power low-jitter PLL clock synthesizer for microprocessors with clock range 200-768 MHz

[摘要] In this article the results of the clock synthesizer development are shown. Different variants of voltage repeater for the system of automatic frequency tuning were analyzed. It was shown that for the purpose of energy consumption and jitter reducing the repeater on peripheral transistor can be used. The synthesizerwas created on the technology with design rules 180 nm. Scaling for the technology with design rules 90 nm is also possible.

[发布机构] National Research Nuclear University, MEPhI (Moscow Engineering Physics Institute), Kashirskoe shosse 31, Moscow; 115409, Russia^1

[关键词] Automatic frequency tuning;Clock synthesizer;Design rules;Low Power