Energy-delay complexity of asynchronous circuits

[摘要] In this thesis, a circuit-level theory of energy-delay complexity is developed for asynchronous circuits. The energy-delay efficiency of a circuit is characterized using the metric Et^n , where E is the energy consumed by the computation, t is the delay of the computation, and n is a positive number that reflects a chosen trade-off betweenenergy and delay. Based on theoretical and experimental evidence, it is argued that for a circuit optimized for minimal Et^n, the consumed energy is independent, in firstapproximation, of the types of gates (NAND, NOR, etc.) used by the circuit and is solely dependent on n and the total amount of wiring capacitance switched during computation. Conversely, the circuit speed is independent, in first approximation, of the wiring capacitance and depends only on n and the types of gates used.The complexity model allows us to compare the energy-delay efficiency of two circuits implementing the same computation. On the other hand, the complexity model itself does not say much about the actual transistor sizes that achieve the optimum. For this reason, the problem of transistor sizing of circuits optimized for Et^n is investigated, as well. A set of analytical formulas that closely approximate the optimal transistor sizes are explored. An efficient iteration procedure that can furtherimprove the original analytical solution is then studied. Based on these results, a novel transistor-sizing algorithm for energy-delay efficiency is introduced.It is shown that the Et^nmetric for the energy-delay efficiency index n ≥ 0 characterizes any optimal trade-off between the energy and the delay of a computation. Forexample, any problem of minimizing the energy of a system for a given target delay can be restated as minimizing Et^n for a certain n. The notion of minimum-energy function is developed and applied to the parallel and sequential composition of circuits in general and, in particular, to circuits optimized through transistor sizing andvoltage scaling. Bounds on the energy and delay of the optimized circuits are computed, and necessary and sufficient conditions are given under which these bounds arereached. Necessary and sufficient conditions are also given under which components of a design can be optimized independently so as to yield a global optimum whencomposed. Through these applications, the utility of the minimum-energy function is demonstrated. The use of this minimum-energy function yields practical insight intoways of improving the overall energy-delay efficiency of circuits.

[发布机构] University:California Institute of Technology;Department:Engineering and Applied Science

[关键词] Computer Science