Most commercially produced integrated circuits are incapable oftolerating manufacturing defects. The area and function of thecircuits is thus limited by the probability of faults occurringwithin the circuit. This thesis examines techniques for usingredundancy in memory circuits to provide fault tolerance and toincrease storage capacity.
A hierarchical memory architecture using multiple Hamming codesis introduced and analysed to determine its resistance tomanufacturing defects. The results of the analysis indicate thatsubstantial yield improvement is possible with relatively modestincreases in circuit area. Also, the architecture makes it possibleto build larger memory circuits than is economically feasiblewithout redundancy.
