Deep sub-micron stud-via technology for superconductor VLSI circuits

[摘要] A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2and approaches the depairing current density of Nb films.

[发布机构] Lincoln Laboratory, Massachusetts Institute of Technology, Lexington; MA; 02420, United States^1

[关键词] Deep sub-micron;Fabrication process;Resolution limits;Size dependence;Superconducting critical current;Superconducting layer;Very large scale integrated;Via technologies