A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

[摘要] A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless andmultirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complexDSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. Thehomogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to itsnearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates timesharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimizationtechnique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardwarecomplexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventionalmodular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphasefilter circuits are also presented. The RSA architecture offers significant flexibility and computationalcapacity for applications that require real time reconfiguration and high-density computing.

[学科分类] 计算机科学（综合）