Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

[摘要] Test power is the major issue for current generationVLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approachin SoC (i.e., use of IP cores in SoC) has further exaggeratedthe test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse availabletechniques. To find the proper solutions for test power reductionstrategy for IP core-based SoC, in this paper, startingfrom the terminology and models for power consumption duringtest, the state of the art in low-power testing is presented. Thepaper contains the detailed survey on various power reductiontechniques proposed for all aspects of testing like external testing,Built-In Self-Test techniques, and the advances in DFT techniquesemphasizing low power. Further, all the available low-powertesting techniques are strongly analyzed for their suitability to IPcore-based SoC.

[学科分类] 电子、光学、磁材料