CONTANGO: Integrated Optimization of SoC Clock Networks

[摘要] On-chip clock networks are remarkable in theirimpact on the performance and power of synchronous circuits, intheir susceptibility to adverse effects of semiconductor technologyscaling, as well as in their strong potential for improvementthrough better CAD algorithms and tools. Existing literatureis rich in ideas and techniques but performs large-scale optimizationusing analytical models that lost accuracy at recenttechnology nodes and have rarely been validated by realisticSPICE simulationson large industry designs. Our work offers a methodology for SPICE-accurate optimizationof clock networks, coordinated to satisfy slew constraintsand achieve best tradeoffs between skew, insertion delay, power,as well as tolerance to variations. Our implementation, calledContango, is evaluated on 45 nm benchmarks from IBM Researchand Texas Instruments with up to 50 K sinks. It outperforms allpublished results in terms of skew and shows superior scalability.

[学科分类] 电子、光学、磁材料