A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

[摘要] This paper presents a systematic methodology for the generation of high-level performance models for analog component blocks. The transistor sizes of the circuit-level implementations of the componentblocks along with a set of geometry constraints applied over them define the sample space. A Haltonsequence generator is used as a sampling algorithm. Performance data are generated by simulatingeach sampled circuit configuration through SPICE. Least squares support vector machine (LS-SVM) isused as a regression function. Optimal values of the model hyper parameters are determined through agrid search-based technique and a genetic algorithm- (GA-) based technique. The high-level models of theindividual component blocks are combined analytically to construct the high-level model of a completesystem. The constructed performance models have been used to implement a GA-based high-level topologysizing process. The advantages of the present methodology are that the constructed models are accuratewith respect to real circuit-level simulation results, fast to evaluate, and have a good generalizationability. In addition, the model construction time is low and the construction process does not requireany detailed knowledge of circuit design. The entire methodology has been demonstrated with a setof numerical results.

[学科分类] 电子、光学、磁材料