νMOS-based Sorter for Arithmetic Applications

[摘要] The capabilities of the conceptual link between threshold gates and sorting networksare explored by implementing some arithmetic demonstrators. In particular, both an(8 × 8)-multiplier and a (15, 4) counter which use a sorter as the main building blockhave been implemented. Traditional disadvantages of binary sorters such as theirhardware intensive nature are avoided by using νMOS circuits. It allows both animproving of previous results for multipliers based on a similar architecture, and toobtain a new type of counter which shows a reduced delay when compared to a conventionalimplementation.

[学科分类] 电子、光学、磁材料