An Edge-endpoint-based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking

[摘要] Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking(DRC) were hobbled by the fact that it is often impractical to build a different rulecheckingASIC each time design rules or fabrication processes change. In this paper, wepropose a configurable hardware approach to DRC. It can garner impressive speedupsover software approaches, while retaining the flexibility needed to change the rule checkeras rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattangeometry checking and a general scalable architecture for DRC. We then demonstrateour approach by applying this architecture to a set of design rules for MOSISSCN4N_SUB process. We have implemented several design rule checks within a singleXilinx XC4013 FPGA and demonstrated overall speedups in excess of 25X over softwaremethods. We have used a Compaq Pamette board to do the hardware prototyping andhave achieved a clock rate of 33 MHz.

[学科分类] 电子、光学、磁材料