Self-checking Synchronous FSM Network Design with Low Overhead

[摘要] A method of a self-checking synchronous Finite State Machine (FSM) network designwith low overhead is developed. Checkers are used only for FSMs, which output linesare at the same time output lines of the network. The checkers observe output lines ofthese FSMs. The method is based on reducing the problem to a self-checking synchronousFSM design. The latter is provided by applying a special description of FSMnamely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-atfault on the FSM poles and gate poles are considered. PLAurealization of FSM allows afactorized or multilevel logic synthesis. They both provide a unidirectional manifestationof the above mentioned faults on the output lines of the corresponding FSMs. Thisrealization also gives rise to a transparency of each component FSM of the network forthe faults. PLAurealization is derived from the State Transition Graph (STG) descriptionof FSMs with using them-out-of-nencoding of its states and insignificantexpanding the products of STG. The problem of replacing an arbitrary synchronousFSM network for the self-checking one with low overhead is discussed.

[学科分类] 电子、光学、磁材料