Design of MOS-translinear Multiplier/Dividers in Analog VLSI

[摘要] A general framework for designing current-mode CMOS analog multiplier/dividercircuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained froma generic second-order MOS translinear loop. Various implementations are proposed,featuring simplicity, favorable precision and wide dynamic range. They can be successfullyemployed in a wide range of analog VLSI processing tasks. Experimentalresults of two versions, based on stacked and folded MOS-translinear loops and fabricatedin a 2.4-μm CMOS process, are provided in order to verify the correctness ofthe proposed approach.

[学科分类] 电子、光学、磁材料