Delay Time Estimation Model for Large Digital CMOS Circuits

[摘要] Delay time estimation in simulation or design verification step during a design cyclehas become more and more important as the meaning of performance prediction. Thispaper proposed a delay estimation model for digital CMOS circuits, which worksin gate-level but the modeling process includes the characteristics of MOSFETs. Thismodel can handle the variation according to the kind of gates, input transition time,output load(fan-out), and transistor sizes of a gate. The procedure to find the generalmodel was that, a delay model for CMOS inverter was extracted first, then it wasextended to other gate by converting it into an equivalent inverter. The resulting modelwas evaluated and compared with SPICE simulation, which showed that the proposedmodel has the accuracy of less than 5% relative error rate to the SPICE results for eachcase and the speed of about 70 times faster than SPICE.

[学科分类] 电子、光学、磁材料