Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors

[摘要] A generic multiplication scheme for the low power VLSI implementation of the DCT isdescribed in this paper. The scheme concurrently processes blocks of cosine coefficientand pixel values during the multiplication procedure, with the aim of reducing the totalswitched capacitance within the multiplier circuit. The cosine coefficients, within eachblock, are manipulated such that some are processed using shift operations only. Theremaining coefficients are presented to the multiplier inputs as a sequence, orderedaccording to bit correlation between successive cosine coefficients. The paper describesthe multiplication scheme, the power evaluation environment used, and presents results,with a number of standard benchmark examples, demonstrating upto 50% power saving.

[学科分类] 电子、光学、磁材料