Low-Power Built-In Self-Test Techniques for Embedded SRAMs

[摘要] The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, arow bank-basedprechargetechnique based on the divided wordline (DWL) architecture is proposed for low-power testing of embeddedSRAMs. The memory cell array is first divided intorow banks. The effectiveness of the row bank-based precharge techniqueis due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge powercan be reduced to1/bof that of the traditional precharge techniques, wherebdenotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BISTdesigns. It is also notable that the inherent low-power characteristics of the DWL architecture canbe preserved. According to experimental results, 48.9% power reduction can be achieved fora 256×256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

[学科分类] 电子、光学、磁材料