Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

[摘要] A variation-tolerant low-power source-synchronous multicycle (SSMC ) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in3D-ICs. SSMC replaces intermediate flip-flops by a source-synchronous synchronizationscheme. Removing the intermediate flip-flops in the SSMC scheme enables better averagingof delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die WID process variations. Monte Carlo circuit simulations show that SSMC eliminates90%of the variation-induced performance degradation in a 6-cycle 9 mm-long 16-bit conventional bus.The proposed multicycle bus scheme also leads to significant energy savings due to eliminating the power-hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitivecoupling has been addressed and solutions are put forward to alleviate it. Circuit simulations ina  65-nm process environment indicate that energy savings up to20%are achievable for a 6-cycle 9 mm long 16-bit bus.

[学科分类] 电子、光学、磁材料