A Programmable Max-Log-MAP Turbo Decoder Implementation

[摘要] In the advent of very high data rates of theupcoming 3G long-term evolution telecommunication systems,there is a crucial need for efficient and flexible turbo decoderimplementations. In this study, a max-log-MAP turbo decoder isimplemented as an application-specific instruction-set processor.The processor is accompanied with accelerating computing units,which can be controlled in detail. With a novel memory interface,the dual-port memory for extrinsic information is avoided. As aresult, processing one trellis stage with max-log-MAP algorithmtakes only 1.02 clock cycles on average, which is comparable topure hardware decoders. With six turbo iterations and 277 MHzclock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.

[学科分类] 电子、光学、磁材料