Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

[摘要] This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm.Coarse-to-fine search approach is employedto find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelinedparallel design with 9 processing elements. Two different methods aredeployed to reduce the power consumption, parallel and pipelined implementation andparallel accessing to memory. For processing 30 CIF frames per second ourarchitecture requires a clock frequency of 4.5 MHz.

[学科分类] 电子、光学、磁材料