Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

[摘要] Dual supply voltage scaling (DSVS) for logiclevelpower optimization at the has increasingly attracted attentionover the last few years. However, mainly due to thefact that the most widely used design tools do not supportthis new technique, it has still not become an integral partof real-world design flows. In this paper, a novel logic synthesismethodology that enables DSVS while relying entirelyon standard tools is presented. The key to this methodologyis a suitably modeled dual supply voltage (DSV) standardcell library. A basic evaluation of the methodology has beencarried out on a number of MCNC benchmark circuits. Inall these experiments, the results of state-of-the-art powerdrivensingle supply voltage (SSV) logic synthesis have beenused as references in order to determine the true additionalbenefit of DSVS. Compared with the results of SSV poweroptimization, additional power reductions of 10% on averagehave been achieved. The results prove the feasibility ofthe new approach and reveal its greater efficiency in comparisonwith a well-known dedicated DSVS algorithm. Finally,the methodology has been applied to an embedded microcontrollercore in order to further explore the potentials andlimitations of DSVS in an existing industrial design environment.

[学科分类] 电子、光学、磁材料