Sparse matrix-vector multiplication on network-on-chip

[摘要] In this paper, we present an idea for performing matrix-vectormultiplication by using Network-on-Chip (NoC) architecture. In traditional ICdesign on-chip communications have been designed with dedicatedpoint-to-point interconnections. Therefore, regular local data transfer isthe major concept of many parallel implementations. However, when dealingwith the parallel implementation of sparse matrix-vector multiplication(SMVM), which is the main step of all iterative algorithms for solving systemsof linear equation, the required data transfers depend on the sparsitystructure of the matrix and can be extremely irregular. Using the NoCarchitecture makes it possible to deal with arbitrary structure of the datatransfers; i.e. with the irregular structure of the sparse matrices. So far,we have already implemented the proposed SMVM-NoC architecture with the size4×4 and 5×5 in IEEE 754 single float point precision usingFPGA.

[学科分类] 电子、光学、磁材料