A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

[摘要] The conventional sensing scheme of single-ended read-only-ports as integratedin 8T-SRAM cells suffers from low performance compared to double-endedcomplementary sensing schemes.In the proposed sensing scheme the pre-charge voltage of thesingle-ended read-bit-line is set to a level above the threshold voltage ofthe sensing device with an adjustable margin.This margin is minimized to speed up the read access on the one hand and keptlarge enough to provide a sufficient bit-line noise margin on the other hand.The pre-charge voltage level of the proposed sensing circuittracks the threshold voltage of the sensing device under process variationsin order to maintain a minimum required bit-line noise margin.To avoid unnecessary bit-line discharging, the proposed sensingscheme employs a modified 8T-SRAM cell.Compared to the conventional 8T-SRAM cell, the read port of the proposedcell provides a virtual ground line running in parallel to the bit-lines.An internal driver of the sensing circuit releases the virtual ground lineduring the evaluation period to prevent the charge dissipation resultingin a raised voltage level.The reduced pre-charge level and the increased virtual ground leadto a reduced bit-line voltage swing and thus a bit-line power reduction.Access time, energy dissipation, and noise margin of the proposed sensingcircuit are compared with conventional sensing circuits from the literaturefor different numbers of memory cells connected to the bit-line.It is shown, that for a specific number of memory cells per bit-line theproposed circuit achieves fastest access time at low power operation.

[学科分类] 电子、光学、磁材料