Reliability analysis of buffer stage in mixed signal application

[摘要] This paper discusses reliability analysis of a buffer circuit targeted for ananalog to digital converter application. The circuit designed in a 32 nmhigh-κ metal gate CMOS technology was investigated by circuitsimulation and sensitivity analysis. This analysis was conducted forrealistic time varying (AC) stress. As aging effects, negative and positivebias temperature instability, conducting and non-conducting hot carrierinjection are taken into consideration. The aging contributions of theseeffects on the different transistors in the buffer circuit and on differentbuffer performance figures are evaluated. Using these results, the impact ofan aged buffer circuit on the performance of a successive approximation ADCcircuit is evaluated. The most severely affected performance due to aging isamplifier offset, which leads to time varying gain error in the ADC circuit.

[学科分类] 电子、光学、磁材料