A modified prefix operator well suited for area-efficient brick-based adder implementations

[摘要] The implementation of integrated circuits becomes more and more difficult inthe Ultra-Deep-Submicron regime due to sub-wavelength lithography issues. Anapproach called Brick-Based Design was recently proposed to eliminate thedisadvantages of staying with the classical approach to layout design. Prefixadders are a core component in a wide variety of applications due to theirhigh speed and regular topology. In this paper, a modified prefix operatorfor prefix adders is proposed which is well suited for brick-style layoutimplementation and, in addition, offers an increase in efficiency. Theproposed operator makes it possible to use a mirror gate for the generationof both generate and propagate signals, which exhibits a forbidden inputsignal combination. This "forbidden state" causes an increase in powerdissipation due to transient short circuit currents. The effect of theforbidden state was quantified as part of a comparison against the classicalprefix operator, based on 64-bit Sklansky adders implemented in a 40-nm CMOStechnology. The effects of the forbidden state were found to be wellacceptable. The implementation of the adder based on the proposed prefixoperator reduces the area by 29% while increasing the power by 13% comparedto one based on the classical operator.

[学科分类] 电子、光学、磁材料