Improved fault tolerance of Turbo decoding based on optimized index assignments

[摘要] This paper investigates the impact of an error-prone buffer memory on achannel decoder as employed in modern digital communication systems. On onehand this work is motivated by the fact that energy efficient decoderimplementations may not only be achieved by optimizations on algorithmiclevel, but also by chip-level modifications. One of such modifications is socalled aggressive voltage scaling of buffer memories, which, while achievingreduced power consumption, also injects errors into the likelihood valuesused during the decoding process. On the other hand, it has been recognizedthat the ongoing increase of integration density with smaller structuresmakes integrated circuits more sensitive to process variations duringmanufacturing, and to voltage and temperature variations. This may lead to aparadigm shift from 100 %-reliable operation to fault tolerant signalprocessing. Both reasons are the motivation to discuss the required co-designof algorithms and underlying circuits. For an error-prone receive buffer of aTurbo decoder the influence of quantizer design and index assignment on theerror resilience of the decoding algorithm is discussed. It is shown that asuitable design of both enables a compensation of hardware induced bitserrors with rates up to 1 % without increasing the computational complexityof the decoder.

[学科分类] 电子、光学、磁材料