50 Gbit/s real-time test environment for integrated photonic DQPSK receivers

[摘要] In this paper an FPGA-based test system for high-speed transmissionexperiments with integrated photonic receivers is presented. Pseudorandombinary sequences are generated inside the FPGA and encoded as eitherdifferential quadrature phase shift keying (DQPSK) or quadrature phase shiftkeying (QPSK) signals. The DQPSK encoder uses a 64-foldparallel-prefix-layers architecture for real-time operation which allows fora maximum internal encoder data rate of 64 Gbit/s. Two-fold paralleldata streams of I and Q signals suitable for driving an optical IQ-modulatorcan be transmitted and received by four 12.5 Gbit/s transceivers.Integrated bit error testers are used to determine bit error rates inreal-time.

[学科分类] 电子、光学、磁材料