A VLSI design concept for parallel iterative algorithms

[摘要] Modern VLSI manufacturing technology has kept shrinking down to the nanoscalelevel with a very fast trend. Integration with the advanced nano-technologynow makes it possible to realize advanced parallel iterative algorithmsdirectly which was almost impossible 10 years ago. In this paper, we want todiscuss the influences of evolving VLSI technologies for iterative algorithmsand present design strategies from an algorithmic and architectural point ofview. Implementing an iterative algorithm on a multiprocessor array, there isa trade-off between the performance/complexity of processors and theload/throughput of interconnects. This is due to the behavior of iterativealgorithms. For example, we could simplify the parallel implementation of theiterative algorithm (i.e., processor elements of the multiprocessorarray) in any way as long as the convergence is guaranteed. However, themodification of the algorithm (processors) usually increases the number ofrequired iterations which also means that the switch activity ofinterconnects is increasing. As an example we show that a 25×25 fullJacobi EVD array could be realized into one single FPGA device with thesimplified μ-rotation CORDIC architecture.

[学科分类] 电子、光学、磁材料