A code-aided synchronization IP core for iterative channel decoders

[摘要] Synchronization and channel decoding are integral parts of each receiver inwireless communication systems. The task of synchronization is the estimationof the general unknown parameters of phase, frequency and timing offset aswell as correction of the received symbol sequence according to the estimatedparameters. The synchronized symbol sequence serves as input for the channeldecoder. Advanced channel decoders are able to operate at very lowsignal-to-noise ratios (SNR). For small values of SNR, the parameterestimation suffers from increased noise and impacts the communicationperformance. To improve the synchronization quality and thus decoderperformance, the synchronizers are integrated into the iterative decodingstructure. Intermediate results of the channel decoder after each iterationare used to improve the synchronization. This approach is referred to ascode-aided (CA) synchronization or turbo synchronization.

A number of CA synchronization algorithms have already been published butthere is no publication so far on a generic hardware implementation of the CAsynchronization. Therefore we present an algorithm which can be implementedefficiently in hardware and demonstrate its communication performance.Furthermore we present a high throughput, flexible, area and power efficientcode-aided synchronization IP core for various satellite communicationstandards. The core is synthesized for 65 nm low power CMOS technology. Afterplacement and routing the core has an area of 0.194 mm², throughputof 207 Msymbols/s and consumes 41.4 mW at 300 MHz clock frequency. Thearchitecture is designed in such a way that it does not affect throughput ofthe system.

[学科分类] 电子、光学、磁材料