High-voltage circuits for power management on 65 nm CMOS

[摘要] This paper presents two high-voltage circuits used in power management, aswitching driver for buck converter with optimized on-resistance and a lowdropout (LDO) voltage regulator with 2-stacked pMOS pass devices. Thecircuit design is based on stacked MOSFETs, thus the circuits are technologyindependent.

High-voltage drivers with stacked devices suffer from slow switchingcharacteristics. In this paper, a new concept to adjust gate voltages ofstacked transistors is introduced for reduction of on-resistance. Accordingto the theory, a circuit is proposed that drives 2 stacked transistors of adriver. Simulation results show a reduction of the on-resistance between27 and 86 % and a reduction of rise and fall times between16 and 83 % with a load capacitance of 150 pF at various supplyvoltages, compared to previous work. The concept can be applied to eachhigh-voltage driver that is based on a number (N) of stacked transistors.
The high voltage compatibility of the low drop-out voltage regulator (LDO)is established by a 2-stacked pMOS transistors as pass device controlled bytwo regulators: an error amplifier and a 2nd amplifier adjusting thedivision of the voltages between the two pass transistors. A high GBW andgood DC accuracy in line and load regulation is achieved by using 3-stageerror amplifiers. To improve stability, two feedback loops are utilized.

In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technologyare used for the circuit design.

[学科分类] 电子、光学、磁材料