Yield-improving test and routing circuits for a novel 3-D interconnect technology
[摘要] This work presents a system to increase the yield of a novel 3-Dchip integration technology. A built-in self-test and a routingsystem have been developed to identify and avoid faults onvertical connections between different stacked chips. The 3-Dtechnology is based on stacking several active CMOS-ICs, whichhave through-substrate electrical contacts to communicate witheach other. The expected defects of these vias are shorts andresistances that are too high.
The test and routing system is designed to analyze an arbitrarynumber of connections. The result ist used to gain informationabout the reliability of the new 3-D processing and to increase itsyield. The circuits have been developed in 0.13 μmtechnology, one chip has been fabricated and tested, another oneis in production.
