Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic

[摘要] Future SoCs will feature embedded FPGAs (eFPGAs) toenable flexible and efficient implementations of high-throughput digitalsignal processing applications. Current research projects on and emergingproducts containing FPGAs are mainly based on "standard FPGA"-architecturesthat are optimised for a very wide range of applications. The implementationcosts of these FPGAs are dominated by a very complex interconnect network.This paper presents a method to improve the efficiency of eFPGAs bytailoring them for a certain application domain using a parametrisablearchitecture template derived from the results of a systematic evaluation ofthe requirements of the application domain.

Two different architectures are discussed, a reference architecture toillustrate the methodology and possible optimisation measures as well as aspecialised arithmetic-oriented eFPGA for applications like correlators,decoders, and filters. For the arithmetic-oriented architecture, a novellogic element (LE) and a special interconnect architecture that was designedwith respect to the connectivity characteristics of regular datapaths, arepresented. For both architecture templates, physically optimisedimplementations based on an automatic design approach have been created.

As a first cost comparison of these implementations with standard FPGAs, theLE-density (number of logic elements per mm²) is evaluated. For thearithmetic-oriented architecture, the LE-density could be increased by anorder of magnitude compared to standard architectures.

[学科分类] 电子、光学、磁材料