Phase noise and jitter modeling for fractional-N PLLs

[摘要] We present an analytical phase noise model for fractional-N phase-locked loops (PLL)with emphasis on integrated RF synthesizers in the GHz range.The noise of the crystal reference, the voltage-controlled oscillator (VCO),the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filteredby the PLL operation. We express the rms phase error (jitter) in terms of phasenoiseof the reference, the VCO phase noise and the third-order loop filter parameters.In addition, we consider OFDM systems, where the PLL phase noise is reducedby digital signal processing after down-conversion of the RF signal to baseband.The rms phase error is discussed as a function of the loop parameters. Our modeldrastically simplifies the noise optimization of the PLL loop dynamics.

[学科分类] 电子、光学、磁材料