Physical IC debug – backside approach and nanoscale challenge

[摘要] Physical analysis for IC functionality in submicron technologies requiresaccess through chip backside. Based upon typical global backside preparationwith 50–100 µm moderate silicon thickness remaining, a state of the artof the analysis techniques available for this purpose is presented andevaluated for functional analysis and layout pattern resolution potential. Acircuit edit technique valid for nano technology ICs, is also presented thatis based upon the formation of local trenches using the bottom of ShallowTrench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As aderivative from this process, a locally ultra thin silicon device can beprocessed, creating a back surface as work bench for breakthroughapplications of nanoscale analysis techniques to a fully functional circuitthrough chip backside. Several applications demonstrate the power andpotential of this new approach.

[学科分类] 电子、光学、磁材料