Impact of on-chip inductance on power supply integrity

[摘要] Based on product related scenarios, the impact of on-chip inductance on power supplyintegrity is analyzed. The impact of varying current profiles is shown to be minimal. In aregular power grid with regular bump connections, the impact of on-chip inductance on the cycleaverage of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance.Whereas, the maximum transient power supply drop can be significantly underestimated by neglecting on-chipinductance. The impact of on-chip inductance in a System-on-Chip (SoC) environment also can be neglectedif the on-chip inductance is conservativly estimated.

[学科分类] 电子、光学、磁材料