Power optimization of digital baseband WCDMA receiver components on algorithmic and architectural level

[摘要] High data rates combined with high mobility represent a challenge for thedesign of cellular devices. Advanced algorithms are required which result inhigher complexity, more chip area and increased power consumption. However,this contrasts to the limited power supply of mobile devices.

This presentation discusses the application of an HSDPA receiver which hasbeen optimized regarding power consumption with the focus on the algorithmicand architectural level. On algorithmic level the Rake combiner,Prefilter-Rake equalizer and MMSE equalizer are compared regarding their BERperformance. Both equalizer approaches provide a significant increase ofperformance for high data rates compared to the Rake combiner which iscommonly used for lower data rates. For both equalizer approaches severaladaptive algorithms are available which differ in complexity and convergenceproperties. To identify the algorithm which achieves the required performancewith the lowest power consumption the algorithms have been investigated usingSystemC models regarding their performance and arithmetic complexity.Additionally, for the Prefilter Rake equalizer the power estimations of amodified Griffith (LMS) and a Levinson (RLS) algorithm have been comparedwith the tool ORINOCO supplied byChipVision. The accuracy of this tool has been verified with a scalablearchitecture of the UMTS channel estimation described both in SystemC andVHDL targeting a 130 nm CMOS standard cell library.

An architecture combining all three approaches combined with an adaptivecontrol unit is presented. The control unit monitors the current condition ofthe propagation channel and adjusts parameters for the receiver like filtersize and oversampling ratio to minimize the power consumption whilemaintaining the required performance. The optimization strategies result in areduction of the number of arithmetic operations up to 70% for singlecomponents which leads to an estimated power reduction of up to 40% whilethe BER performance is not affected.

This work utilizes SystemC and ORINOCO forthe first estimation of power consumption in an early step of the designflow. Thereby algorithms can be compared in different operating modesincluding the effects of control units. Here an algorithm having higher peakcomplexity and power consumption but providing more flexibility showed lessconsumption for normal operating modes compared to the algorithm which isoptimized for peak performance.

[学科分类] 电子、光学、磁材料