Fast evaluation of nonlinear functions using FPGAs

[摘要] The paper presents a novel method of evaluating the square root function inFPGA. The method uses a linear approximation subsystem with a reduced sizeof a look-up table. The reduction in the size of the lookup table istwofold. Firstly, a simple linear approximation subsystem uses the lookuptable only for the node points. Secondly, a concept of a variable steplook-up table is introduced, where the node points are not uniformly spaced,but the spacing is determined by how close to the linear function theapproximated function is. The proposed method of evaluating nonlinearfunction and specifically the square root function is practical for wordlengths of up to 24 bits. The evaluation is performed in one clock cycle.

[学科分类] 电子、光学、磁材料