Comparison of reconfigurable structures for flexible word-length multiplication

[摘要] Binary multiplication continues to be one of the essential arithmeticoperations in digital circuits. Even though field-programmable gate arrays(FPGAs) are becoming more and more powerful these days, the vendors cannotavoid implementing multiplications with high word-lengths using embeddedblocks instead of configurable logic. But on the other hand, the circuit'sefficiency decreases if the provided word-length of the hard-wiredmultipliers exceeds the precision requirements of the algorithm mapped intothe FPGA. Thus it is beneficial to use multiplier blocks with configurableword-length, optimized for area, speed and power dissipation, e.g. regardingdigital signal processing (DSP) applications.

In this contribution, we present different approaches and structures for therealization of a multiplication with variable precision and perform anobjective comparison. This includes one approach based on a modified Baugh andWooley algorithm and three structures using Booth's arithmetic operandrecoding with different array structures. All modules have the option tocompute signed two's complement fix-point numbers either as an individualcomputing unit or interconnected to a superior array. Therefore, a highthroughput at low precision through parallelism, or a high precision throughconcatenation can be achieved.

[学科分类] 电子、光学、磁材料