An 8 bit current steering DAC for offset compensation purposes in sensor arrays

[摘要] An 8 bit segmented current steering DAC is presented for the compensation ofmismatch of sensors with current output arranged in a large arrays. The DACis implemented in a 1.8 V supply voltage 180 nm standard CMOS technology.Post layout simulations reveal that the design target concerning a samplingfrequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns.The output current range is 0–10 μA, which translates into anLSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB andDNL < 0.4 LSB, respectively. Static power consumption with the outputsoperated at a voltage of 0.9 V is approximately 10 μW. Dynamicpower, mainly consumed by switching activity of the digital circuit parts,amounts to 100 μW at 2.6 MHz operation frequency. Total area is38.6 × 2933.0 μm².

[学科分类] 电子、光学、磁材料