Design space exploration of high throughput finite field multipliers for channel coding on Xilinx FPGAs

[摘要] Channel coding is a standard technique in all wireless communication systems.In addition to the typically employed methods like convolutional coding,turbo coding or low density parity check (LDPC) coding, algebraic codes areused in many cases. For example, outer BCH coding is applied in the DVB-S2standard for satellite TV broadcasting. A key operation for BCH and therelated Reed-Solomon codes are multiplications in finite fields (GaloisFields), where extension fields of prime fields are used. A lot ofarchitectures for multiplications in finite fields have been published overthe last decades. This paper examines four different multiplier architecturesin detail that offer the potential for very high throughputs. We investigatethe implementation performance of these multipliers on FPGA technology in thecontext of channel coding. We study the efficiency of the multipliers withrespect to area, frequency and throughput, as well as configurability andscalability. The implementation data of the fully verified circuits areprovided for a Xilinx Virtex-4 device after place and route.

[学科分类] 电子、光学、磁材料