The Fabrication and Evaluation of Silicon MOSFETs With 0.5 to 0.1 Micron Gate Lengths

[摘要] This Thesis describes the application of high resolution electron beam lithography and dry etching techniques to the fabrication of experimental silicon MOSFETs with sub 0.5 micron gate lengths. HRN, a negative electron beam resist is investigated and demonstrated to have a resolution of 0.1 microns. Two alternative dry etching processes are reported for patterning 0.1 micron polysilicon gate electrodes using HRN masking. The first process uses chlorine plasma etching whilst the second process uses silicon tetrachloride reactive ion etching. MOSFET scaling theory is introduced and then used as a guide for designing the experimental sub 0.5 micron devices. A full processing sequence is developed for fabricating the experimental devices. This process includes self-aligned ion implantation and rapid thermal annealing steps, to form the shallow source and drain drift regions. Devices with gate oxide thicknesses of 150 angstroms and channel doping levels in the range from 3x10e16 to 1.2x10e18 atoms/cm3 have been implemented. Electrical measurements are reported for the range of devices which have been fabricated. Results are included for MOSFETs with gate lengths of only 0.11 microns. At a channel doping level of 1.2x10e18 atoms/cm3 the 0.11 micron devices exhibit a transconductance of 70 mS/mm. A slightly modified process is described which has been used to implement a second set of sub 0.5 micron devices together with 19 stage unloaded n-MOS ring oscillator circuits. Preliminary high speed measurements are reported for these circuits which have gate lengths of 0.23 microns. Minimum stage delays of 80 psec have been achieved with a corresponding power-delay product of 210 fJ.

[发布机构] University:University of Glasgow

[关键词] Electrical engineering