Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems

[摘要] As networks become more versatile, the computational requirement for supporting additionalfunctionality increases. The increasing demands of these networks can be met by Field ProgrammableGate Arrays (FPGA), which are an increasingly popular technology for implementing packet processingsystems. The fine-grained parallelism and density of these devices can be exploited to meet thecomputational requirements and implement complex systems on a single chip. However, the increasingcomplexity of FPGA-based systems makes them susceptible to errors and difficult to test and debug.To tackle the complexity of modern designs, system-level languages have been developed to provideabstractions suited to the domain of the target system. Unfortunately, the lack of formality inthese languages can give rise to errors that are not caught until late in the design cycle. Thisthesis presents three techniques for verifying and validating FPGA-based packet processing systemsdescribed in a system-level description language. First, a type system is applied to the systemdescription language to detect errors before implementation. Second, system-level transactionmonitoring is used to observe high-level events on-chip following implementation. Third, thehigh-level information embodied in the system description language is exploited to allow the systemto be automatically instrumented for on-chip monitoring.This thesis demonstrates that these techniques catch errors which are undetected by traditionalverification and validation tools. The locations of faults are specified and errors are caughtearlier in the design flow, which saves time by reducing synthesis iterations.

[发布机构] University:University of Glasgow;Department:School of Engineering

[关键词] validation, verification, FPGA, packet processing