On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits.

[摘要] The VLSI industry has achieved advancement in technology by continuous processscaling which has resulted in large scale integration. However, scaling also poses newreliability challenges. Currently the industry ensures the reliability of chips by limitingthe supply voltage and temperature, but these constraints limit the benefits that areobtained from new process nodes. This method of managing reliability during designtime is called Static Reliability Management (SRM). While SRM ensures that all thechips meet the reliability specifications, it introduces extreme pessimism in the chips as itmargins for worst process, voltage, temperature and circuit state (PVTS), which will notbe required for the majority of chips. To reduce the pessimism of SRM, the system needsto be made aware of its reliability by employing degradation sensors or degradationdetection techniques. Using the degradation measurements, the system can estimate itslifetime and can adjust its operating points (supply voltage and temperature limits)dynamically and trade excess reliability slack with performance. This method ofreliability management is called Dynamic Reliability Management (DRM).In this work we investigate different methods of DRM. We focus on two criticaldegradation mechanisms: Negative Bias Temperature Instability (NBTI) and Gate-oxidedegradation. We propose NBTI and Gate-oxide degradation sensors with low area andpower overhead, which allows them to be deployed in large numbers on the chip enablingcollection of degradation statistics. The sensors were designed in 130nm and 45nmprocess nodes and tested on two test-chips. We then used the sensors to perform DRM ina silicon test for the first time. We demonstrate that DRM eliminates excess reliabilityslack which allows for a boost in supply voltage and performance.We then propose in situ Bias Temperature Instability (BTI) and Gate-oxide wear-outdetection techniques. The in situ technique measures the degradation in the actual devicesin the core and removes all the layers of uncertainty which arise because of the statisticalnature of degradation and its dependence on PVTS. We implemented and tested thesetechniques on two test chips in a 65nm process node. We then use the BTI sensingtechnique to perform DRM.

[发布机构] University of Michigan

[效力级别] Bias Temerature Instability (BTI)

[关键词] VLSI Circuit Reliability;Bias Temerature Instability (BTI);Gate-oxide Wear-out;Sensor;Dynamic Reliability Management;In Situ Sensing;Electrical Engineering;Engineering;Electrical Engineering